The present invention relates generally to electroless plating. More particularly, the present invention relates to back-end-of-line (BEOL) microelectronic device fabrication. In one particular embodiment, the present invention relates to cobalt electroless plating in the fabrication of interconnect structures in semiconductor devices.
Cobalt electroless processes have been used in the semiconductor industry. Miniaturization is the process of reducing the size of semiconductor devices, while crowding more devices onto a relatively smaller area of a substrate. One challenge in electroless plating processes is to keep the process flow simple while still achieving the sometimes complex chemical demands required to accomplish the plating process.
During semiconductor wafer fabrication, multiple levels of conductive layers are formed above a substrate. The multiple metallization layers are employed in order to accommodate higher densities as device dimensions shrink well below one micrometer (micron) design rules. Thus, semiconductor structures having six levels of metallization (the sixth level being referred to as metal-six or M6) or more are becoming more prevalent as device geometries shrink to sub-micron levels.
One common metal used for forming metal lines, also referred to a metallization or wiring on a wafer is aluminum. Aluminum is used because it is relatively inexpensive compared to other conductive materials, it has low resistivity and is relatively easy to etch. Aluminum is also used as a material for forming interconnections in vias to connect the different metal layers. However, as the size of via/contact holes is scaled down to a sub-micron region, the step coverage becomes a problem. Poor step coverage in the sub-micron via/contact holes results in high current density and makes electromigration worse.
One material which has received considerable attention as a replacement material for VLSI interconnect metallizations is copper. Since copper has better electromigration properties and lower resistivity than aluminum, it is preferred. In addition, copper plugs have more improved electrical properties over tungsten plugs. However, a disadvantage of using copper metallization is that it is difficult to etch. Accordingly, one practice has been to utilize chemical-mechanical polishing (CMP) techniques to polish away the unwanted copper material. Another concern with the use of copper as interconnect material is its diffusion properties. Accordingly, diffusion barrier metals are used, such as titanium nitride (TiN), tantalum nitride (TaN), or titanium tungsten (TiW), as well as dielectric barrier materials, such as silicon nitride (SiN) and silicon carbide (SiC).
To replace the tungsten and aluminum plugs with copper plugs in VLSI or in ultra large-scale integration (ULSI) manufacturing, another important factor to consider is the process cost. The technique of selectively depositing copper within the via holes to form the plugs is attractive, because it eliminates the polishing (CMP) step. One technique of selectively depositing metals, is the use of electroless deposition. In comparison to other deposition techniques, electroless deposition is attractive due to the low processing cost and high quality of metal deposited. However, electroless deposition requires the activation of a surface in order to electrolessly deposit the metal, such as cobalt. Additionally, electroless deposition requires complicated, multi-component chemistries that pose both control and replenishment challenges due to the many and varied components.